Product |
Comments |
---|---|
Cisco ONS 15454 |
Timing Communications Control (TCC) card Building Integrated Timing Supply (BITS) output General Release 2.0.2 (Formerly Cerent 454) |
Using version 2.0.2 software, the TCC may not provide correct external BITS output.
This problem was discovered during testing.
This problem does not affect service. An incorrect BITS clock output may be seen when using system software version 2.0.2. The BITS input will not synchronize with the BITS output, causing BITS to stop providing an output signal.
This problem is isolated to the external BITS output; systems that are line timed are not affected. This problem only affects nodes that are receiving incoming DS1 BITS and sourcing outgoing DS1 BITS at the same time.
If this problem is experienced, perform a software warm reset of the TCCs using Call Management System (CMS). To perform a warm reset:
Right click Standby TCC in the CMS node view.
From the popup menu select reset.
After the TCC has booted up and is in Standby mode, right click Active TCC and select reset.
When the Active TCC resets, you will experience a side switch.
This problem is fixed in a future software load.
This defect has Cisco bug ID CSCdp91239. To follow the bug ID link below and see detailed bug information, you must be a registered user and you must be logged in.
DDTS |
Description |
---|---|
Resolved in next GA release |
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