Overview
The Precision Time Protocol (PTP), as defined in the IEEE 1588 standard, synchronizes with nanosecond accuracy the real-time clocks of the devices in a network. The clocks are organized into a server-client hierarchy. PTP identifies the port that is connected to a device with the most precise clock. This clock is referred to as the server clock. All the other devices on the network synchronize their clocks with the server and are referred to as members. Constantly-exchanged timing messages ensure continued synchronization. PTP ensures that the best available clock is selected as the source of time (the grandmaster clock) for the network and that other clocks in the network are synchronized to the grandmaster.
Network Element |
Description |
---|---|
Grandmaster (GM) |
A network device physically attached to the primary time source. All clocks are synchronized to the grandmaster clock. |
Ordinary Clock (OC) |
An ordinary clock is a 1588 clock with a single PTP port that can operate in one of the following modes:
|
Boundary Clock (BC) |
The device participates in selecting the best server clock and can act as the server clock if no better clocks are detected. Boundary clock starts its own PTP session with a number of downstream clients. The boundary clock mitigates the number of network hops and results in packet delay variations in the packet network between the Grandmaster and client. |
Transparent Clock (TC) |
A transparent clock is a device or a switch that calculates the time it requires to forward traffic and updates the PTP time correction field to account for the delay, making the device transparent in terms of time calculations. |
PTP consists of two parts:
-
The port State machine and Best Master Clock Algorithm: This provides a method to determine the ports in the network that will remain passive (neither server nor client), run as a server (providing time to other clocks in the network), or run as clients (receiving time from other clocks in the network).
-
Delay-Request/Response mechanism and a Peer-delay mechanism: This provides a mechanisms for client ports to calculate the difference between the time of their own clocks and the time of their server clock.
Note
Cisco ASR 9000 Series routers do not support Peer-delay mechanism.
The implementation of PTP on Cisco IOS XR software is designed to operate effectively in Telecommunication networks, which are different from the networks for which PTP was originally designed.
PTP is configurable on Gigabit Ethernet interfaces (1G, 10G, 40G, and 100G), Bundle Ethernet interfaces, and sub-interfaces. PTP is not configurable on LAG Ethernet sub-interfaces.
Frequency and Time Selection
The selection of the source to synchronize the backplane clock frequency is made by frequency synchronization, and is outside of the scope of PTP. The Announce, Sync, and Delay-request frequencies must be the same on the server and client.
Delay-Response Mechanism
The Delay Request-response mechanism (defined in section 11.3 of IEEE Std 1588-2008) lets a client port estimate the difference between its own clock-time and the clock-time of its server. The following options are supported:
-
One-step mechanism - The timestamp for a Sync message is sent in the Sync message itself.
-
Two-step mechanism - The timestamp for a Sync message is sent later in a Follow-up message.
When running a port in client state, a router can send Delay-request messages and handle incoming Sync, Follow-up, and Delay-response messages. The timeout periods for both Sync and Delay-response messages are individually configurable.
Hybrid Mode
Your router allows the ability to select separate sources for frequency and time-of-day (ToD). Frequency selection can be between any source of frequency available to the router, such as: BITS, GPS, SyncE or IEEE 1588 PTP. The ToD selection is between the source selected for frequency and PTP, if available (ToD selection is from GPS, DTI or PTP). This is known as hybrid mode, where a physical frequency source (BITS or SyncE) is used to provide frequency synchronization, while PTP is used to provide ToD synchronization.
Frequency selection uses the algorithm described in ITU-T recommendation G.871, and is described in the Configuring Frequency Synchronization module in this document. The ToD selection is controlled using the time-of-day priority configuration. This configuration is found under the source interface frequency synchronization configuration mode and under the global PTP configuration mode. It controls the order for which sources are selected for ToD. Values in the range of 1 to 254 are allowed, with lower numbers indicating higher priority.
Port States
State machine indicates the behavior of each port. The possible states are:
State |
Description |
---|---|
INIT |
Port is not ready to participate in PTP. |
LISTENING |
First state when a port becomes ready to participate in PTP: In this state, the port listens to PTP servers for a (configurable) period of time. |
PRE-MASTER |
Port is ready to enter the Server state. |
MASTER |
Port provides timestamps for any client or boundary clocks that are listening. |
UNCALIBRATED |
Port receives timestamps from a server clock but, the router’s clock is not yet synchronized to the server. |
SLAVE |
Port receives timestamps from a server clock and the router’s clock is synchronized to the server. |
PASSIVE |
Port is aware of a better clock than the one it would advertise if it was in server state and is not a client clock to that server clock. |
Leap Seconds
In prior releases, IOS-XR only offered a static and time-consuming solution to manage leap seconds. For every upcoming leap second inclusion, the number of leap seconds had to be hard-coded into a Software Maintenance Update (SMU) and also installed on the router for the same. It is a prolonged and tedious process to provide and install a SMU each time a new leap second is announced.
From Release 6.4.1 onward, Cisco IOS-XR supports leap-second configuration instead of SMU installations or reloads.
Time is measured using a common timescale. Leap second factor is used to adjust the current time to compensate for any drift from the common timescale. Leap seconds are introduced to dynamically adjust the UTC offset in response to leap second events. The two most relevant timescales are:
-
TAI - International Atomic Time : This is a notional passage of time determined by weighted average of readings across a large number of atomic clocks.
-
UTC - Universal Coordinated Time : This differs from TAI by an integer number of seconds to remain in synchronization with mean solar time. UTC is related to a notion of time called UT1, which represents the mean solar time at 0° longitude. Leap seconds are periodically inserted to ensure UTC and UT1 are never more than 0.9 seconds apart.
PTP uses TAI timescale. UTC time is derived using UTC offset. UTC offset and the number of seconds in the last minute of the current UTC day are sent in the PTP header of Announce messages.
UTC is calculated as: UTC = TAI - offset .
IOS-XR PTP implementation uses the following sources (in order of decreasing precedence) to determine the current UTC offset value:
-
The current grandmaster clock, if present.
-
UTC offset configuration, if present.
-
The previous grandmaster clock, if one exists.
-
The hardware (e.g. a locally connected GPS receiver), if available.
-
Zero, indicating that no UTC offset information is available.
If any upcoming leap second (being advertised at the time synchronization with a grandmaster) is lost, that too will be applied at the appropriate time while in holdover
Note |
|
Multiple PTP Profile Interoperability
Communication between two different profiles was not possible previously due to various factors like, incompatible domain numbers, BMCA, or clock-class leading to drop in packets. Also, you cannot compare devices running different profiles in such configurations. For example, the domain number for G.8275.1 profile (24) is incompatible with the domain number for G.8275.2 profile (44).
Multiple PTP Profile Interoperability feature lets you develop a configuration to communicate with a peer device running a different PTP profile than the profile that is configured on the source router. This means that multiple profiles can interoperate on a single device in this implementation.
Interoperation is achieved by converting packets on ingress/egress so that it is acceptable to the profile configured on the receiving device. This prevents packet loss and allows comparison of different profiles. You can configure the interoperation using the interop command. Configuration details are described in a later section in this chapter. For command details, refer to Precision Time Protocol (PTP) Commands chapter in the System Management Command Reference for Cisco ASR 9000 Series Routers guide.
Note |
|
Class C Timing Mode
Feature Name |
Release Information |
Feature Description |
---|---|---|
Class C Timing Mode |
Release 7.6.2 |
We now support the enhanced timing mode, Class C, as per the revised version of G.8273.2 by ITU-T. You can now switch to this Class C mode to avail high-accuracy clocks in the telecom networks having precise timing requirements, such as 5G networks. Class C mode reduces the Maximum Absolute Time Error (Max|TE|) and enhances synchronization of Telecom Boundary Clock (T-BC) and Telecom Time Secondary Clock (T-TSC). Class C timing support is available for both PTP and Frequency Synchronization. Class C timing mode is supported only on the routers with the combination of following Route Switch Processors (RSPs) and Fifth generation of the ASR 9000 Series Ethernet line cards except A99-32X100GE-X-TR/SE:
This feature introduces the timing-accuracy enhanced command. |
The advent of 5G technology demands strict timing requirements. To satisfy the strict timing requirements, ITU-T has introduced Class C or Enhanced timing accuracy mode under G8273.2 profile. Class B or Legacy mode is the default mode. The Max|TE| for Class B is 70 ns, whereas for Class C it is 40 ns. Reduced Max|TE| error indicates reduced noise transfer and improved timing accuracy between T-BC and T-SC.
Restrictions
-
Class C timing support is not available on A99-32X100GE-X-TR/SE Lightspeed-plus-based line card.
-
Class C is not supported on the following line cards:
-
BITS-output clock does not work with Cisco IOS XR Software Release 7.6.2 image. You must install Software Maintenance Updates (SMU) for the same.
-
If the timing-accuracy enhanced command is applied on the router with unsupported line cards, the timing functionality stops working on those line cards.
The following system log appears on the router console when Class C configuration is applied on the routers containing unsupported hardware that does not support Class C mode.
LC/0/1/CPU0:Sep 2 15:51:50.791 UTC: sync_agent[325]: %PLATFORM-FSYNC-4-CLOCK_ACCURACY_UNSUPPORTED : This line card does not support enhanced accuracy mode
To configure Class C mode, see Configuring Class C Timing Mode.
PTP Phase Difference Threshold Between Passive and Secondary Ports
Feature Name |
Release Information |
Feature Description |
---|---|---|
PTP Phase Difference Threshold Between Passive and Secondary Ports |
Release 24.2.1 |
Passive ports can now be included in the Delay Request-Response Mechanism (DRRM), which allows for the monitoring of PTP phase differences between a passive port and a secondary port. If these PTP phase differences surpass a predefined limit, system logs are triggered. This feature enables you to detect potential errors such as fiber asymmetry or a clock failure in the PTP network. This feature introduces these changes: CLI:
YANG Data Models: The following data models are enhanced:
|
The Precision Time Protocol (PTP), as defined in the IEEE 1588 standard, is designed for precise time synchronization across networked devices. It operates by having Foreign Masters (FMs) broadcast timing information to interfaces within the network. The selection of the Grandmaster (GM), the primary reference clock, is determined by the Best Master Clock Algorithm (BMCA). Devices synchronize their clocks to the GM through a process known as the Delay Request-Response Mechanism (DRRM), wherein ports that are directly synchronizing with the GM enter a secondary state.
Historically, ports in a passive state—those that receive timing messages from FMs but aren’t actively syncing to the GM—didn’t participate in DRRM, which meant they didn’t synchronize their clocks.
Starting Cisco IOS XR Software Release 24.2.1, DRRM has been extended to include passive ports, enabling them to engage in the exchange of delay request and response packets. This enhancement allows for the calculation of PTP phase differences between the clocks on passive ports and the GM.
This calculated PTP phase difference provides a valuable insight into the timing characteristics of other foreign masters in the network by using the grandmaster as a reference point. It can be utilized on any boundary clock or slave clock that has connections to at least one other foreign master.
You can access these measurements and the calculated PTP phase differences using show commands through the router's CLI. Also, the information can be retrieved programmatically through operational data models in YANG, providing flexibility in how you can access and utilize this synchronization data.
Phase Difference Alarm
PTP phase difference can also be used to monitor the timing properties of the network. You can configure a value at which a bistate alarm is triggered when the PTP phase difference of a FM exceeds the threshold. The PTP phase difference can have a negative or positive value, but the threshold can only be the absolute value. You can configure the PTP phase difference threshold using the phase-difference-threshold-breach command.
System Log for PTP Phase Difference
When the configured threshold is reached, system logs (syslogs) are displayed. The following syslog is triggered if the configured PTP phase difference threshold is passed through by any master.
Phase difference for clock ACDE48FFFE234567, steps removed 1, receiving-port 1, received on interface GigabitEthernet0/2/0/3 is 40ns, configured threshold is 30ns. Raising phase difference alarm.
Configure PTP Phase Difference Alarm Threshold
Procedure
Step 1 |
Configure threshold for triggering PTP phase difference alarms using the phase-difference-threshold-breach command. Example:
|
Step 2 |
Verify that PTP phase difference threshold value is configured using the show running configuration command. Example:
|
Step 3 |
Display the current operational value using the show ptp foreign-masters command. Example:
|
Isolate Foreign Masters Causing Packet Timing Signal Fail
Feature Name |
Release Information |
Feature Description |
---|---|---|
Isolate Foreign Masters Causing Packet Timing Signal Fail |
Release 24.2.1 |
This feature permits the flexible selection of timing sources by filtering out Foreign Master (FM) clocks that exhibit unstable timing. This filtering causes the secondary clocks to produce a signal deemed Packet Timing Signal Fail (PTSF)-unusable, from consideration within the Best Master Clock Algorithm (BMCA). The system continuously monitors these clocks for timing stabilization, and upon detecting enhanced stability, it may reevaluate and possibly reintegrate them as suitable time sources. This feature introduces these changes: CLI:
YANG Data Models: The following data models are enhanced:
|
Starting Cisco IOS XR Software Release 24.2.1, the servo mechanism now has the ability to detect unusable clocks due to packet timing signal fail by analyzing timestamps from foreign masters. This enhancement allows the system to identify foreign masters with unstable timing as unsuitable for use. A platform supports multiple masters, such a master can be excluded from the BMCA selection process while remaining under observation for potential recovery. Even after a master is deemed unusable, the DRRM continues to operate and timestamps from it are still provided to the servo. This ongoing monitoring enables PTP to detect and respond to any improvements in the primary's timing, allowing it to be reconsidered as usable.
System Log for PTSF-unusable
When the master becomes PTSF-unusable, and if its the current Grandmaster, the following system log (syslogs) is displayed:
Foreign master with clock ID ACDE48FFFE234567, steps removed 1, receiving-port 1, received on interface GigabitEthernet0/2/0/4 is now PTSF-unusable and disqualified from selection.
Configure PTSF-unusable
Procedure
Step 1 |
Exclude the FM with unstable timing from selection in the BMCA and declare it as unusable using the detect-ptsf-unusable command. Example:
|
Step 2 |
Check if the master clock is PTSF-unuable using the show ptp foreign-masters command. Example:
|
PTP Support Information
This table lists different types of support information related to PTP:
Transport Media |
|
Messages |
|
Transport Modes |
|
PTP Hardware Support Matrix
Feature Name |
Release Information |
Feature Description |
---|---|---|
Precision Time Protocol on 12-port 100 Gigabit Ethernet line cards, ASR 9000 5th generation 400G line cards, ASR 9902 Series Routers, and 0.8T PEC |
Release 7.4.1 |
Support for IEEE-1588 PTP is extended to the following routers and line cards:
|
PTP support on 5th Generation 10-Port 400 Gigabit Ethernet Line Cards:
|
Release 7.3.2 |
Support for IEEE-1588 PTP is extended to the following line cards:
|
Note |
The table also contains support details of upcoming releases. You can read this table in context of the current release and see relevant Release Notes for more information on supported features and hardware. |
This table provides a detailed information on the supported hardware:
Hardware Variant |
1588/PTP |
Cisco IOS XR |
Cisco IOS XR 64 bit |
Comments |
---|---|---|---|---|
A9K-8X100GE-L-SE/TR (10GE and 100GE) |
Default & G.8265.1 |
5.3.3 |
6.3.2 6.4.1 |
PTP over Ethernet does not work on 100G ports on Cisco IOS XR until 6.4.1. Support was introduced in 6.4.1. |
G.8275.1 & G.8275.2 |
6.2.1 |
6.3.2 6.4.1 |
||
G.8273.2 |
6.2.1 |
6.3.2 |
||
PTP Multiprofile |
6.5.1 |
6.5.1 |
||
A9K-RSP880-SE/TR |
1588/PTP Default & G.8265.1 |
5.3.3 |
6.3.2 6.4.1 |
- |
1588/PTP G.8275.1 & G.8275.2 |
6.2.1 |
6.3.2 6.4.1 |
||
1588/PTP G.8273.2 |
6.2.1 |
6.3.2 6.4.1 |
||
PTP Multiprofile |
6.5.1 |
6.5.1 |
||
A9K-8X100GE-L-SE/TR (40-GE) |
1588/PTP Default & G.8265.1 |
6.0.1 |
6.3.2 6.4.1 |
- |
1588/PTP G.8275.1 & G.8275.2 |
6.2.1 |
6.3.2 6.4.1 |
||
1588/PTP G.8273.2 |
NA |
NA |
||
PTP Multiprofile |
6.5.1 |
6.5.1 |
||
A9K-4X100GE-SE/TR A9K-8X100GE-SE/TR |
1588/PTP Default & G.8265.1 |
6.2.1 |
6.4.1 |
PTP over Ethernet does not work on 100G ports on Cisco IOS XR until 6.4.1. Support was introduced in 6.4.1. In 6.2.1, only G.8275.1 PTP profile is supported on the cards; No support for G.8273.2 PTP profile. |
1588/PTP G.8275.1 & G.8275.2 |
6.2.1 |
6.4.1 |
||
1588/PTP G.8273.2 |
6.4.1 |
6.4.1 |
||
PTP Multiprofile |
6.5.1 |
6.5.1 |
||
A9K-MOD400-SE/TR & A9K-MOD200-SE/TR with Legacy MPAs |
1588/PTP Default & G.8265.1 |
6.1.3 |
6.4.1 |
- |
1588/PTP G.8275.1 & G.8275.2 |
6.2.2 |
6.4.1 |
- |
|
1588/PTP G.8273.2 |
- |
- |
- |
|
PTP Multiprofile |
6.5.1 |
6.5.1 |
- |
|
A9K-MOD400-SE/TR & A9K-MOD200-SE/TR with MPA 20x10GE , A9K-MPA-1X100GE and A9K-MPA-2X100GE |
1588/PTP Default & G.8265.1 |
6.1.3 |
6.4.1 |
PTP over Ethernet does not work on 100G ports on Cisco IOS XR until 6.4.1. Support was introduced in 6.4.1. In 6.2.2, only G.8275.1 PTP profile is supported on the cards. No support for G.8273.2 PTP profile until 6.5.1. |
1588/PTP G.8275.1 & G.8275.2 |
6.2.2 |
6.4.1 |
||
1588/PTP G.8273.2 |
6.5.1 |
6.5.1 |
||
PTP Multiprofile |
6.5.1 |
6.5.1 |
||
A9K-24X10GE-1G-SE/TR A9K-48X10GE-1G-SE/TR |
1588/PTP Default & G.8265.1 |
6.2.2 6.3.1 |
6.3.2 |
- |
1588/PTP G.8275.1 & G.8275.2 |
6.2.2 6.3.1 |
6.3.2 |
||
1588/PTP G.8273.2 |
6.3.1 |
6.3.2 |
||
PTP Multiprofile |
6.5.1 |
6.5.1 |
||
A99-RSP-SE/TR (Cisco ASR 9910 Series Routers) |
1588/PTP Default & G.8265.1 |
6.3.1 |
6.3.2 |
- |
1588/PTP G.8275.1 & G.8275.2 |
6.3.1 |
6.3.2 |
||
1588/PTP G.8273.2 |
6.4.1 |
6.3.2 |
||
PTP Multiprofile |
6.5.1 |
6.5.1 |
||
A9K-RSP880-LT-SE/TR |
1588/PTP Default & G.8265.1 |
6.2.2 |
6.4.1 |
- |
1588/PTP G.8275.1 & G.8275.2 |
6.2.2 |
6.4.1 |
||
1588/PTP G.8273.2 |
6.4.1 |
6.4.1 |
||
PTP Multiprofile |
6.5.1 |
6.5.1 |
||
A9K-RSP440-TR/SE A99-RP-SE Enhanced Ethernet Linecards |
1588/PTP Default & G.8265.1 |
4.3.4 |
NA |
Enhanced Ethernet linecards do not support G.8273.2 with G.8275.1 PTP profile. . |
1588/PTP G.8275.1 & G.8275.2 |
NA |
NA |
||
1588/PTP G.8273.2 |
NA |
NA |
||
A99-RP2-TR/SE |
1588/PTP Default & G.8265.1 |
5.3.3 |
6.3.2 6.4.1 |
- |
1588/PTP G.8275.1 & G.8275.2 |
6.2.1 |
6.3.2 6.4.1 |
||
1588/PTP G.8273.2 |
NA |
NA |
||
Cisco ASR 9001 Series Routers |
1588/PTP Default & G.8265.1 |
4.3.4 |
NA |
Enhanced Ethernet based hardware does not support G.8273.2 with G.8275.1 PTP profile. |
1588/PTP G.8275.1 & G.8275.2 |
NA |
NA |
||
1588/PTP G.8273.2 |
NA |
NA |
||
Cisco ASR 9901 Series Routers |
1588/PTP Default & G.8265.1 |
NA |
6.4.1 |
- |
1588/PTP G.8275.1 & G.8275.2 |
NA |
6.4.1 |
||
1588/PTP G.8273.2 |
NA |
6.6.1 |
||
PTP Multiprofile |
NA |
6.5.1 |
||
A99-RSP-SE/TR (Cisco ASR 9906 Series Routers) |
1588/PTP Default & G.8265.1 |
6.3.1 |
6.3.2 |
- |
1588/PTP G.8275.1 & G.8275.2 |
6.3.1 |
6.3.2 |
||
1588/PTP G.8273.2 |
6.4.1 |
6.3.2 |
||
PTP Multiprofile |
6.5.1 |
6.5.1 |
||
A9K-RSP5-SE |
1588/PTP Default & G.8265.1 |
NA |
6.5.15 |
- |
1588/PTP G.8275.2 |
NA |
6.5.15 |
||
1588/PTP G.8275.1 & G.8273.2 |
NA |
6.6.1 |
||
PTP Multiprofile |
NA |
6.5.15 |
||
A9K-RSP5-TR |
1588/PTP Default & G.8265.1 |
NA |
6.5.15 |
- |
1588/PTP G.8275.2 |
NA |
6.5.15 |
||
1588/PTP G.8275.1 & G.8273.2 |
NA |
6.6.1 |
||
PTP Multiprofile |
NA |
6.5.15 |
||
A99-RP3-SE |
1588/PTP Default & G.8265.1 |
NA |
6.5.15 |
- |
1588/PTP G.8275.2 |
NA |
6.5.15 |
||
1588/PTP G.8275.1 & G.8273.2 |
NA |
6.6.1 |
||
PTP Multiprofile |
NA |
6.5.15 |
||
A99-RP3-TR |
1588/PTP Default & G.8265.1 |
NA |
6.5.15 |
- |
1588/PTP G.8275.2 |
NA |
6.5.15 |
||
1588/PTP G.8275.1 & G.8273.2 |
NA |
6.6.1 |
||
PTP Multiprofile |
NA |
6.5.15 |
||
A9K-8X100GE-X-TR |
1588/PTP Default & G.8265.1 |
NA |
6.5.15 |
- |
1588/PTP G.8275.2 |
NA |
6.5.15 |
||
1588/PTP G.8275.1 & G.8273.2 |
NA |
6.6.1 |
||
PTP Multiprofile |
NA |
6.5.15 |
||
A9K-16X100GE-TR |
1588/PTP Default & G.8265.1 |
NA |
6.5.15 |
NA |
1588/PTP G.8275.2 |
NA |
6.5.15 |
||
1588/PTP G.8275.1 & G.8273.2 |
NA |
6.6.1 |
||
PTP Multiprofile |
NA |
6.5.15 |
||
A99-16X100GE-X-SE A99-32X100GE-TR/CM |
1588/PTP Default & G.8265.1 |
NA |
6.6.1 |
NA |
1588/PTP G.8275.2 |
NA |
6.6.1 |
||
1588/PTP G.8275.1 & G.8273.2 |
NA |
6.6.1 |
||
PTP Multiprofile |
NA |
6.6.1 |
||
A9K-32X100GE-TR |
1588/PTP Default & G.8265.1 |
NA |
6.5.15 |
- |
1588/PTP G.8275.2 |
NA |
6.5.15 |
||
1588/PTP G.8275.1 & G.8273.2 |
NA |
6.6.1 |
||
PTP Multiprofile |
NA |
6.5.15 |
||
Cisco ASR 9903 Series Routers |
1588/PTP Default & G.8265.1 |
NA |
7.1.3 |
You must configure ‘one-step’ clock operation on the PTP master interface. |
1588/PTP G.8275.2 |
NA |
7.1.3 |
||
1588/PTP G.8275.1 & G.8273.2 |
NA |
7.1.3 |
||
PTP Multiprofile |
NA |
NA |
||
A9903-20HG-PEC |
1588/PTP Default & G.8265.1 |
NA |
7.1.3 |
|
1588/PTP G.8275.2 |
NA |
7.1.3 |
||
1588/PTP G.8275.1 & G.8273.2 |
NA |
7.1.3 |
||
PTP Multiprofile |
NA |
NA |
||
A99-32X100GE-X-SE/TR |
1588/PTP Default & G.8265.1 |
NA |
7.1.15 |
|
1588/PTP G.8275.2 |
NA |
7.1.15 |
||
1588/PTP G.8275.1 & G.8273.2 |
NA |
7.1.15 |
||
PTP Multiprofile |
NA |
NA |
||
A9K-8HG-FLEX-SE/TR |
1588/PTP Default & G.8265.1 |
NA |
7.1.15 |
You must configure ‘one-step’ clock operation on the PTP master interface. |
1588/PTP G.8275.2 |
NA |
7.1.15 |
||
1588/PTP G.8275.1 & G.8273.2 |
NA |
7.1.15 |
||
PTP Multiprofile |
NA |
NA |
||
A9K-20HG-FLEX-SE/TR |
1588/PTP Default & G.8265.1 |
NA |
7.1.15 |
You must configure ‘one-step’ clock operation on the PTP master interface. |
1588/PTP G.8275.2 |
NA |
7.1.15 |
||
1588/PTP G.8275.1 & G.8273.2 |
NA |
7.1.15 |
||
PTP Multiprofile |
NA |
NA |
||
A99-10X400GE-X-SE/TR |
1588/PTP Default & G.8265.1 |
NA |
7.3.2 |
You must configure ‘one-step’ clock operation on the PTP master interface. Class B Performance (Applicable to 1588/PTP G.8275.1 & G.8273.2) |
1588/PTP G.8275.2 |
NA |
7.3.2 |
||
1588/PTP G.8275.1 & G.8273.2 |
NA |
7.3.2 |
||
PTP Multiprofile |
NA |
NA |
||
A99-12x100GE A99-12X100GE-CM |
1588/PTP Default & G.8265.1 |
NA |
7.4.1 |
|
1588/PTP G.8275.2 |
NA |
7.4.1 |
||
1588/PTP G.8275.1 & G.8273.2 |
NA |
7.4.1 |
Class B Performance |
|
PTP Multiprofile |
NA |
7.4.1 |
||
A99-8X100GE-SE/TR/CM A9K-8X100GE-CM A9K-8X100G-LB-SE/TR A9K-400G-DWDM-TR A99-48X10GE-1G-SE/TR |
1588/PTP Default & G.8265.1 |
6.2.2 |
6.2.2 |
|
1588/PTP G.8275.2 |
6.2.2 |
6.2.2 |
||
1588/PTP G.8275.1 & G.8273.2 |
6.2.2 |
6.2.2 |
||
PTP Multiprofile |
6.2.2 |
6.2.2 |
||
A9K-4X100GE |
1588/PTP Default & G.8265.1 |
NA |
7.4.1 |
|
1588/PTP G.8275.2 |
NA |
7.4.1 |
||
1588/PTP G.8275.1 & G.8273.2 |
NA |
7.4.1 |
Class B Performance |
|
PTP Multiprofile |
NA |
NA |
||
A9K-400GE-SE/TR |
1588/PTP Default & G.8265.1 |
NA |
7.4.1 |
|
1588/PTP G.8275.2 |
NA |
7.4.1 |
||
1588/PTP G.8275.1 & G.8273.2 |
NA |
7.4.1 |
Class B Performance |
|
PTP Multiprofile |
NA |
NA |
||
A99-400GE-SE/TR |
1588/PTP Default & G.8265.1 |
NA |
7.4.1 |
|
1588/PTP G.8275.2 |
NA |
7.4.1 |
||
1588/PTP G.8275.1 & G.8273.2 |
NA |
7.4.1 |
Class B Performance |
|
PTP Multiprofile |
NA |
NA |
||
ASR 9902 |
1588/PTP Default & G.8265.1 |
NA |
7.4.1 |
Port 12 to Port 35 provides Class B Performance and requires two-step clock operation on PTP master interface Port 0 to port 11 and port 36 to port 47 provide Class C performance and requires one-step clock operation on PTP master interface. |
1588/PTP G.8275.2 |
NA |
7.4.1 |
||
1588/PTP G.8275.1 & G.8273.2 |
NA |
7.4.1 |
||
PTP Multiprofile |
NA |
NA |
||
ASR-9903 |
1588/PTP Default & G.8265.1 |
NA |
7.4.1 |
You must configure ‘one-step’ clock operation on the PTP master interface. |
1588/PTP G.8275.2 |
NA |
7.4.1 |
||
1588/PTP G.8275.1 & G.8273.2 |
NA |
7.4.1 |
||
PTP Multiprofile |
NA |
NA |
||
A9K-4HG-FLEX-SE/TR |
1588/PTP Default & G.8265.1 |
NA |
7.4.1 |
You must configure ‘one-step’ clock operation on the PTP master interface. |
1588/PTP G.8275.2 |
NA |
7.4.1 |
||
1588/PTP G.8275.1 & G.8273.2 |
NA |
7.4.1 |
||
PTP Multiprofile |
NA |
7.4.1 |
||
A99-4HG-FLEX-SE/TR |
1588/PTP Default & G.8265.1 |
NA |
7.4.1 |
You must configure ‘one-step’ clock operation on the PTP master interface. |
1588/PTP G.8275.2 |
NA |
7.4.1 |
||
1588/PTP G.8275.1 & G.8273.2 |
NA |
7.4.1 |
||
PTP Multiprofile |
NA |
7.4.1 |
Note |
The following 2nd generation line cards support all IEEE-1588 PTP telecom profiles (Default, G.8265.1, G.8275.2, G.8275.1, G.8273.2, and PTP Multiprofile) in Cisco IOS XR 32 bit:
|
Restrictions
-
PTP Grandmaster (GM) is not supported with all the PTP profiles.
-
RSP IEEE 1588 port on RSP/RP is not supported.
-
Two-step clock operation is recommended over one-step clock operation for a PTP server.
-
If PTP clock operation CLI is not configured, the default clock operation is two-step on all ASR9000 hardware variants.
-
Due to the difference in PTP timestamp unit, which involves the PHY injecting the timestamp instead of the NPU, you must configure PTP clock operation one-step on the PTP master interface of the line cards which are explicitly specified in the PTP Hardware Support Matrix. Rest of the line cards only support PTP clock operation two-step on the PTP master interface.
-
PTP clock operation one-step or two-step restriction is only for PTP master interface. PTP slave interface can operate in either one-step or two-step.
-
Cisco ASR 9000 Series Routers do not support Class B 1 Pulse Per Second (PPS) performance with Forward Error Correction (FEC) enabled optics.
-
The upgrade of TimingIC-X firmware impacts timing functionality on the ASR 9902 and ASR 9903 Routers, and 5th Generation Line Cards. You must reload the linecard after upgrade of timing firmware for proper functioning of SyncE and PTP features. Interface flapping and traffic drops are expected during this process.
-
G.8275.1 and G.8275.2 profiles are not supported on Cisco ASR 9001 chassis, Cisco ASR 9000 Ethernet line cards, Cisco ASR 9000 Enhanced Ethernet line cards, and A9K-400G-DWDM-SE/TR line cards.
-
As recommended in Appendix VI of ITU-T G.8275.1 document, G.8275.1 profile is supported only on Bundle Link Aggregation (LAG) member links and not supported on a bundle interface.
-
G.8273.2 Telecom Boundary Clock (T-BC) performance is not supported on 40G interfaces.
-
The G.8273.2 Class B performance is observed when the same type of line card is used for both PTP server and PTP client ports. Class A performance is observed when different types of line cards are used for PTP server and PTP client on T-BC.
-
G.8275.2 profile is supported on Cisco ASR 9000 Series Routers. However, the performance standards of this profile are not aligned with any of the ITU-T standards because performance specifications for G.8275.2 profile has not yet been made available by ITU-T.
-
Transparent Clock (TC) is not supported.
-
PTP Multiprofile is not supported for G.8273.2 Class B performance.
-
Platform Fault Manager (PFM) alarms for the 10MHz port are not supported on A9K-RSP5-SE, A9K-RSP5-TR, A99-RP3-SE, and A99-RP3-TR.
-
Select 5th generation line cards (A9K-20HG-FLEX-xx and A9K-8HG-FLEX-xx) will support PTP Telecom Profile G.8275.2 in combination with transit G.8265.1/G.8275.2 packets, in a future version of these cards.
Note |
Forwarding PTP packets as IP or MPLS isn’t possible without the redirecting device not being PTP-aware. If each node across the PTP path isn’t performing the T-BC function, timing accuracy can’t be maintained. |