Overview
Frequency or timing synchronization is the ability to distribute precision frequency around a network. In this context, timing refers to precision frequency, not an accurate time of day. Precision frequency is required in next generation networks for applications such as circuit emulation.
To achieve compliance to ITU specifications for TDM, differential method circuit emulation must be used, which requires a known, common precision frequency reference at each end of the emulated circuit. The incumbent example of frequency synchronization is provided by SDH equipment. This is used in conjunction with an external timing technology to provide synchronization of precision timing across the network.
SDH equipments are widely replaced by Ethernet equipments and synchronized frequency is required over such Ethernet ports. Synchronous Ethernet (SyncE) is used to accurately synchronize frequency in devices connected by Ethernet in a network. SyncE provides level frequency distribution of known common precision frequency references to a physical layer Ethernet network.
To maintain SyncE links, a set of operational messages are required. These messages ensure that a node is always deriving timing information from the most reliable source and then transfers the timing source quality information to clock the SyncE link. In SDH networks, these are known as Synchronization Status Messages (SSMs). SyncE uses Ethernet Synchronization Message Channel (ESMC) to provide transport for SSMs.
Source and Selection Points
Frequency Synchronization implementation involves Sources and Selection Points.
A Source inputs frequency signals into a system or transmits them out of a system. There are four types of sources:
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Line interfaces. This includes SyncE interfaces and SONET interfaces.
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Clock interfaces. These are external connectors for connecting other timing signals, such as BITS, UTI and GPS.
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PTP clock. If IEEE 1588 version 2 is configured on the router, a PTP clock may be available to frequency synchronization as a source of the time-of-day and frequency.
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Internal oscillator. This is a free-running internal oscillator chip.
Each source has a Quality Level (QL) associated with it which gives the accuracy of the clock. This QL information is transmitted across the network using ESMC or SSMs contained in the SDH frames. This provides information about the best available source the devices in the system can synchronize to. To define a predefined network synchronization flow and prevent timing loops, you can assign priority values to the sources on each router. The combination of QL information and user-assigned priority levels allow each router to choose a source to synchronize its SyncE or SDH interfaces, as described in the ITU standard G.781.
A Selection Point is any point where a choice is made between several frequency signals and possibly one or many of them are selected. Selection points form a graph representing the flow of timing signals between different cards in a router running Cisco IOS XR software. For example, there can be one or many selection points between different Synchronous Ethernet inputs available on a single line card. This information is forwarded to a selection point on the RSP, to choose between the selected source from each card.
The input signals to the selection points can be:
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Received directly from a source.
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Received as the output from another selection point on the same card.
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Received as the output from a selection point on a different card.
The output of a selection point can be used in a number of ways, like:
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To drive the signals sent out of a set of interfaces.
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As input into another selection point on a card.
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As input into a selection point on an another card.
Use show frequency synchronization selection command to see a detailed view of the different selection points within the system.
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SyncE Hardware Support Matrix
This table provides details on the harware that supportes SyncE:
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The table also contains support details of upcoming releases. You can read this table in context of the current release and see relevant Release Notes for more information on supported features and hardware. |
Feature Name |
Release Information |
Feature Description |
---|---|---|
SyncE Support on 5th Generation 10-Port 400 Gigabit Ethernet Line Cards:
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Release 7.3.2 |
Frequency Synchronization is used to distribute precision frequency around a network. Frequency is synchronized accurately using Synchronized Ethernet (SyncE) in devices connected by Ethernet in a network. SyncE is now supported on the line cards:
|
Hardware Variant |
Cisco IOS XR |
Cisco IOS XR 64 bit |
---|---|---|
A9K-8X100GE-L-SE/TR (10GE and 100GE) |
5.3.0 |
6.1.1 |
A9K-RSP880-SE/TR |
5.3.0 |
6.1.1 |
A9K-8X100GE-L-SE/TR (40-GE) |
6.0.1 |
6.1.1 |
A9K-4X100GE-SE/TR A9K-8X100GE-SE/TR |
5.3.2 (100G LAN only) 6.0.1 |
6.1.1 |
A9K-MOD400-SE/TR A9K-MOD200-SE/TR with MPA 20x10GE and Legacy MPAs |
6.0.1 |
6.2.2 |
A9K-MOD400-SE/TR A9K-MOD200-SE/TR with MPAs 2x100 and 1x100 |
6.1.3 |
6.2.2 |
A9K-400G-DWDM-TR |
5.3.3 6.0.1 |
|
A9K-24X10GE-1G-SE/TR A9K-48X10GE-1G-SE/TR |
6.2.1 |
6.3.2 |
A99-RSP-SE/TR (Cisco ASR 9910 Series Routers) |
6.1.4 |
6.3.2 |
RSP880-LT-SE/TR |
6.2.2 |
6.4.1 |
A9K-RSP440-TR/SE Enhanced Ethernet Linecards A99-RP-SE |
4.3.4 |
|
A99-RP2-TR/SE |
5.3.0 |
6.3.2 6.4.1 |
Cisco ASR 9001 Series Routers |
4.3.4 |
|
Cisco ASR 9901 Series Routers |
NA |
6.4.1 |
A99-RSP-SE/TR (Cisco ASR 9906 Series Routers) |
6.3.1 |
6.3.2 |
A9K-RSP5-SE/TR |
NA |
6.5.15 |
A99-RP3-SE/TR |
NA |
6.5.15 |
A9K-8X100GE-X-TR |
NA |
6.5.15 |
A9K-16X100GE-TR |
NA |
6.5.15 |
A9K-32X100GE-TR |
NA |
6.5.15 |
A99-32X100GE-X-TR |
NA |
7.1.15 |
A9K-8HG-FLEX-SE/TR |
NA |
7.1.15 |
A9K-20HG-FLEX-SE/TR |
NA |
7.1.15 |
ASR-9903 |
NA |
7.1.3 |
A9903-20HG-PEC |
NA |
7.1.3 |
A99-10X400GE-X-SE/TR |
NA |
7.3.2 |
A99-12X100GE |
NA |
7.4.1 |
A9K-4X100GE |
NA |
7.4.1 |
ASR-9902 |
NA |
7.4.1 |
A9K-4HG-FLEX-SE/TR |
NA |
7.4.1 |
A99-4HG-FLEX-SE/TR |
NA |
7.4.1 |
SyncE Restrictions
This section lists a few restrictions in configuring frequency synchronization. They are:
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On SyncE line interfaces, you can configure multiple interfaces for SyncE input. However, only one interface from each PHY gets selected as best source and programmed as SyncE input (there is no restriction on SyncE output) on the A9K-24X10GE-1G-SE/TR and A9K-48X10GE-1G-SE/TR line cards.